OpenHBMC
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OVGN
Open-source high performance AXI4-based HyperRAM memory controller
Hello Does OpenHBMC support Infineon HyperRAM chips?
the current version does not work with Vivado 2022.2 steps to reproduce: take GIT files, create project in 2020.2, change constraints compile test with real hardware CR00107 all working open...
Iserdese3 doesn't support 6:1 ratio...could go with a 4x clock and 8:1, but that seems like overkill. Is there a reason behind going to 3x clock rather than 2x?
This is now very bad issue. Sorry folks. After switching from BUFG mode BUFR/BUFIO mode we did see it working well, but just in case we let the loop test...
Hi, we have implemented OpenHBMC on a custom board, it seemed to work well, the memory test passed, passed, passed... but I did run the memory test manually a few...
Looks like HyperRAM 3.0 is upcomming: https://www.infineon.com/cms/en/product/memories/psram-pseudostatic-dram/ We are going to get twice wider data bus width, i.e. 16 bit at 200MHz = 800Mbit/s per chip Part datasheet: https://www.infineon.com/dgdl/Infineon-Data_Sheet_HYPERRAM-DataSheet-v01_00-EN.pdf?fileId=8ac78c8c80027ecd018050aef7544588 OpenHBMC...
Hi, Has anyone got OpenHBMC working for Trenz TE=0725 board? I have been trying to get this to work for days, but no luck, the cypress chip onboard(8M) needs 0...
Narrow bursts with axlen >= 1 are not supported yet. This is quite rare operation mode, though I have plans to support this feature too to keep IP core 100%...
Hello I use a 64 Mbit Hyper-RAM as Microblaze main memory and use a SREC boot-loader to load the program from a QSPI flash memory. Most of the time everything...
Hello, i have an xc7z Zynq as an Equivalent to the artix 7 and want to disable the DDR and use a HyperRam in some run-Modes for power optimization. The...
