NikLeberg
NikLeberg
As stated in #8 output while converting the graph representation of a crash to code is interleaved with informal output from GraphFuzz. This change aims to separate the output by...
Hi there. I noticed, that when converting the graph to the code representation with `./fuzz_write`, informal output from `schema.hpp` is also present in the output: ``` [*] Loading: schema.json [*]...
related #1463 # Context, Motivation & Description Spinal now checks the names of components and declarations for validity in the currently active language. If an invalid name is found, it...
As discussed in #1426 I see great benefit in supporting GHDL as formal backend (actually SymbiYosys+Yosys+GHDL). This very simple PR introduces a new selectable backend `FormalConfig.withSymbiYosysAndGhdl`. By itself this is...
When the `spinal.core.formal.GlobalClock()` is used, an invalid name is given to the signal in VHDL. Which generates with VHDL to: ```vhdl signal _global_clk : std_logic; attribute gclk of _global_clk :...
Hi there, not an issue more of a question. Currently for formal verification SymbiYosys and Verilog/SystemVerilog are used. As documented [here](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Formal%20verification/index.html#formal-primitives) this is somewhat _limited_ to boolean `assert` `cover` and...
Hey there @djyde Thanks for this, it works flawlessly. Small heads-up: In the docs for the jekyll integration there is a small error: https://github.com/djyde/cusdis/blob/7bcf25611de75f52b337a9bb2e6b3f931822f56c/public/doc/integration/jekyll.md?plain=1#L15 It should be: ```html data-page-url="{{ site.url...