hdlConvertorAst

hdlConvertorAst copied to clipboard

Verilog or System Verilog：How could I get the pure Verilog code without System Verilog syntax?

1

Hello, I want to use HDL AST to generate **Verilog (not System Verilog)**, but I am **worried that whether the converted file will have System Verilog specific syntax**. I see...

Hovennnnn

SystemVerilog: multiple packed dimensions not processed correctly

2

If I have a port declaration with multiple packed and unpacked dimensions: ` input logic [P_PACKED0:0][P_PACKED1:0][P_PACKED2:0] multi_dim_input [0:P_UNPACKED0][0:P_UNPACKED1],` only the first packed dimension is recognised as the port's packed dimension,...

theo-scott

https://github.com/Nic30/hdlConvertorAst/blob/master/hdlConvertorAst/hdlAst/_statements.py#L100 elifs property can be used instead, it would simplify the code analysis as code for elifs has to be there and if then block behaves just as another elif...

Nic30