Verilog or System Verilog：How could I get the pure Verilog code without System Verilog syntax?

[Hovennnnn]

Hello, I want to use HDL AST to generate Verilog (not System Verilog), but I am worried that whether the converted file will have System Verilog specific syntax. I see the class name in the code is "ToVerilog2005", and I know Verilog2005 is a subset of SystemVerilog. So, I just guess that you are using Verilog2005 to be compatible with both Verilog and SystemVerilog. Is my guess correct? If not, how could I get the pure Verilog code (not System Verilog)? Thank you so much.

[Nic30]

Hello @Hovennnnn,

do you want to check that the output file contains only Verilog-2005 compatible code or do you want to translate System Verilog syntax to Verilog-2005?

hdlConvertorAst is a library which contains universal AST nodes for (System) Verilog/VHDL. It has some examples of how to implement traslation/transpilation but can not perform SV -> Verilog in general case. (If you need the second one see https://github.com/zachjs/sv2v)

The conversion of AST to code is 1:1 it means that if you put SV feature in AST you will obtain SV if you restrict yourself to Verilog the output will be Verilog.