hdlConvertor

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Convert VHDL package to Verilog or SV

2

I have VHDL package files in my current directory which I'd like to convert to Verilog or SV using hdlConvertor. Is this possible? As in the [notebook example](https://github.com/Nic30/hdlConvertor/blob/master/notebooks/01_parse_and_dump.ipynb), I'm able...

jabate-anova

Verilog2017 - unpacked array converted as packed

2

Hi, it seems that HdlConvertor does not preserve the dimensions of array when parsing the module interface. See the example below: **example.sv:** ```verilog module test ( logic [0:10] packed_array, logic...

diffore

incorrect Position

6

Hello Position return by the tool is incorrect: include.vh: ``` input a ``` test.v: ``` module my_module( `include "include.vh" ); endmodule ``` test.py ``` from hdlConvertorAst.language import Language from hdlConvertor...

Thomasb81

Preprocessor - expose complete parser?

12

I can see that the way hdlConverter works is that it first passes the code through a preprocessor. Then produces and AST from the resulting text. This preprocessor 'flattens' the...

the-moog

Question regarding VHDL to hwt

3

Hi, I' like to tranfer a larger VHDL Library to hwt. I've had a look at test_verilog_to_hwt.py, which does exactly what I need but unfortunatelly for Verilog. In analogy to...

kaidoho

Handling extraneous commas (SystemVerilog)

1

Existing code, which synthesises and simulates fine in Xilinx and Synopsys toolchains fails with hdlConverter. The issue is extraneous commas in module parameter definitions and module instance signal connections. This...

the-moog

Replace scikit-build/cmake with mesonpep517/meson (potential drop of python2.7 support)

1

The meson buildsystem together with mesonpep517 can make hdlConvertor working out of the box with minimal effort and maintenance. An example of use: https://github.com/ev-br/mc_lib. (there is no `setup.py`, there is...

Nic30

[test_hier_delay_value.sv.tar.gz](https://github.com/Nic30/hdlConvertor/files/7384509/test_hier_delay_value.sv.tar.gz) SystemVerilog grammar of hdlConvertor failed to parse the attached testcase. Apparently following syntax is right... LRM seems incomplete. the syntax is accepted and simulation is run by several commercial...

Thomasb81

SystemVerilog import package - doesn't seem to do anything?

8

Hi, I'm trying to use hdlConvertor to discover all the files I need in my file list. (If someone has already done this please let me know :) ) So...

flemish4

The hdlConvertor rules for parsing of the comments are following. * All comments directly before current object are interpreted as a doc of an object * The comments after an...

Nic30