MarioOpenHWGroup

[CI] cva6.py in Github CI

20

Change the current Github CI to use `cva6.py`

### Is there an existing CVA6 task for this? - [X] I have searched the existing task issues ### Task Description Currently, the Github CI utillizes the Makefile directly with...

Add tohost capabilities to cv32e20 environment

1

Add tohost mechanism instead of the in-house one that we had to end the tests.

[CSR] Fix bits when RVS and RVU not available

5

Disable some bits when RVU or RVS not present

Bump verif/core-v-verif from f7bda8e to NOTMERGED

13

PR for the incoming changes to core-v-verif (not already merged)

Many fix for riscv-isa-sim

2

* Fix MISA for cva6 (b bit) * Add YAML report * Add MIP injection * Fix parameter extensions * Add halt from riscv-isa-sim * Fix riscv-isa-sim version when starts...

Improvements on the RVFI tracer to enable interrupt injection and correct CSRs comparison