MarioOpenHWGroup

Looks good :+1:

After reproducing the issue, I have realized that there is a missing parameter for the `zicntr` extension which is not by default active in Spike. In my opinion all the...

Yes Spike can be configured adding the `zicntr` to the ISA string. In my opinion as this is an extension should be treated as it is, yes. I noticed that...

Already merged by @zchamski https://github.com/openhwgroup/core-v-verif/pull/2334

It is ready to merge, but a review of the changes would be appreciated :smile:

A working version of the Tandem has been pushed to my repo that implements the following: - Tandem comparing exceptions, interrupts, destination GPR, instruction and pc. - Common package that...

Tandem rebased to last cva6/master commit. It is working on Centos 7 and Debian 10. Some discussion needed regarding integration `corev_apu/tb/common/Sim*.cc` into riscv-isa-sim

Fixing Github CI in order to merge. Also fixing the issues commented in both PRs.

CI has been fixed and it shows green on Thales CI and on Github

PR has been merged already