mipt-mips
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MIPT-ILab
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
sbrk is a system call inside malloc. To run interesting programs, it should be supported inside MARSKernel class. The idea is to keep pool of free heap memory in same...
We have a detailed description of [BPU model](https://github.com/MIPT-ILab/mipt-mips/wiki/BPU-model), but it does not cover interaction with pipeline and process of flush. New manual should answer these questions: 1. What are the...
MIPS ISA defines that TLB miss is handled by OS. TLB miss should generate an exception, which is handled by OS exception handler, which manipulates TLB using TLB-manipulating instructions (tlbp,...
GDBWrapper class is an interface responsible for communication with GDB in remote simulation mode. It has to be covered with unit tests, please implement them here: https://github.com/MIPT-ILab/mipt-mips/blob/master/simulator/export/gdb/gdb_wrapper.h
Follows #918 RISC-V Proxy Kernel is a handler of RISC-V system calls (https://github.com/riscv/riscv-pk). The ultimate goal is to enable it as one of available MIPT-V kernels, likewise MARS. The implementation...
Please follow: * https://github.com/MIPT-ILab/mipt-mips/wiki/Data-Bypass-and-Scoreboard * https://github.com/MIPT-ILab/mipt-mips/wiki/Unit-Tests * Lecture 8; Advanced Pipelining The idea is to model pipeline in a small scale: ```c++ DataBypass db( 7); MIPS32Instr load( "ld"); load->dst =...
TBD
Follows #413. Based on the manual of #413, create unit tests in `mips32_memory_test` file and implement the instructions to match the test.
Follows #626 and #613. Delayed branches should be supported by PerfSim as well. The idea is not quite simple: * [ ] branch misprediction should not cancel previous instruction (or...
Worth to start with #530! MIPSInstr has a lot of methods like `is_jump()`, `is_load()`, `is_conditional_move()` etc. These methods may be easily tested in a following manner ```c++ TEST_CASE( "MIPS_instr: Test_Mul")...