Mostafa Rady

Counters - Timers documentation issue

1

Table 16 of the counter [documentation ](https://caravel-harness.readthedocs.io/en/latest/counter-timers.html) isn't aligned with the description inside the test cases. Bits description inside test cases: ``` /* Timer configuration bits: */ /* 0 =...

pwr_ctrl_out register doesn't have reset value

1

register `pwr_ctrl_out` inside `housekeeping.v` is always undefined because the register never gets reset. possible solution is to add: ``` if (porb == 1'b0) begin ... ... ... pwr_ctrl_out

VCS error due to defining default net type as none for primitives

3

## Expected Behavior VCS compile the library Verilog files ## Actual Behavior VCS throws errors like this for primitives ``` Identifier 'SET' has not been declared yet. If this error...

I managed to compile and simulate caravel with verilator while removing the chip io. Since verilator still can't compile any buffer with drive strength, we could replace chip_io with behavior...

openframe user wrapper uses all the power domain

1

openframe_project_wrapper definition inside [caravel_openframe](https://github.com/efabless/caravel/blob/e6169aaf8c1989696aace38eabed13e2b2bc4362/verilog/rtl/caravel_openframe.v#L222) forces the user project to use all of the 6 power domains which complicates the PnR and introduces issues to the LVS.

efabless io modules doesn't have a guard for USE_POWER_PINS

2

some of `_ef_` modules under` sky130_fd_io.v` don't consider the case of simulating without `USE_POWER_PINS`.

Please remove this branch after merging. fix for https://github.com/efabless/caravel_user_project/issues/347

Simulation with VexRISC is so slow

10

The simulation with the `riscV (VexRISC) ` cpu is way slower than `swift2`. `Swift2 `is faster more than 4 times. This may be because `riscV (VexRISC) `cpu doesn't have cache...

management gpio pull up and down doesn't work

10

management gpio registers `reg_gpio_mode1` and `reg_gpio_mode0` don't have an affect in the value of gpio_in_core when floating.