Mostafa Rady

Hi, Any updates about this problem ?

It works because the default net type in verilog is wire. So if the default net type doesn't change any net with no definition would considered as a wire. The...

@RTimothyEdwards , Yes they are outdated. I was suppose to remove them from caravel since I moved the whole cocotb running scripts outside caravel into [caravel-sim-infrastructure](https://github.com/efabless/caravel-sim-infrastructure). All the needed documentation...

The location for adding the tests are under the user project repo not caravel repo. Until caravel and the soc is combined, I use the same flow that the user...

modules like: - sky130_ef_io__vddio_hvc_clamped_pad - sky130_ef_io__vddio_hvc_clamped_pad - sky130_ef_io__vdda_hvc_clamped_pad - sky130_ef_io__vssa_hvc_clamped_pad - sky130_ef_io__vccd_lvc_clamped_pad - sky130_ef_io__vssd_lvc_clamped_pad - sky130_ef_io__top_power_hvc. not sure if these are all the modules with ports issue when `USE_POWER_PINS` isn't...

Can you provide more information about what are you trying to do and when did you face this issue?

You can ignore this failure for now it's not a real error. we will take of it soon.

Updated the make file for running cocotb. The flow will not work directly for now as the makefile cloning mpw-9 caravel and litex but cocotb needs the recent updates at...

Matt pull request would fix the issue @marwaneltoukhy could you merge it?

I debugged this example with @mo-hosni. We found out the wishbone interface isn't blocking the simulation the ack for any user write or read is asserted after 1 cycle. We...