Lucas Bragança

Slice in Wire with two dimension

1

Hi, I'm trying to do the following structure in Veriloggen: ``` m = Module('test') my_wire0 = m.Wire('my_wire0',8,2) my_wire1 = m.Output('my_wire1',2) my_wire1.assign(my_wire0[0][0:2]) print(m.to_verilog()) ``` But an exception is raised!