Lucas Bragança

Hi, this would be something like this: ``` from veriloggen import * def make_module(): m = Module('xval') i_xval = m.Input('i_xval',12,signed=True) e_xval = m.Wire('e_xval',15,signed=True) e_xval.assign(Cat(i_xval[11],i_xval,Repeat(Int(0,1,2),2))) return m print(make_module().to_verilog()) ```