KyleJeong

Results 5 issues of KyleJeong

Fsdb annotation method needs to be update

I am happy with Vcd dump, but Fsdb could be better for VCS(with Verdi) debugging. So I tried to change the Vcd to Fsdb like as. ~~~ test().withAnnotations(Seq(WriteFsdbAnnotation) ~~~ But...

Support of wire declaration for the instance ports.

6 comment

before (assume that user copied the port declaration to top) input clk, input [2:0] in_a, input [2:0] in_b, output reg [3:0] out_sum module module_name ( input clk, input [2:0] in_a,...

verilog parser - Wrong parsing of comment

In below case, the parser think "0", "Time", "1", and "Freq" are ports. I don't know which line make it confuse. To prevent that I added two "(r'/\*', 'block_comment', 'block_comment'),"...

verilog parser - parse as a port of a function's port.

I have a module which include a function in a module. In that cases, it thought 'value' and 'lshift' are ports. module xxx ( aaa ); output reg [1:0] aaa;...

verilog parser - parsing when port name has "input_" characters

This was the case I met. input wire [29:0] input_data; In that case, parser though that the port name is "_data".