vim-verilog-instance
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antoinemadec
Support of wire declaration for the instance ports.
before (assume that user copied the port declaration to top) input clk, input [2:0] in_a, input [2:0] in_b, output reg [3:0] out_sum module module_name ( input clk, input [2:0] in_a, input [2:0] in_b, output reg [3:0] out_sum ); ... end module after (assume the user execute the wire declaration on top and execute the instantiation on buttom) wire clk; wire [2:0] in_a; wire [2:0] in_b; wire [3:0] out_sum; module module_name ( .clk(clk), .in_a(in_a), .in_b(in_b), .out_sum(out_sum) ); ... end module If we can do that in one command, it will be better definetely.
Here is what needs to be done:
- put all the code in verilog_instance.py (do not create a new file, use a script argument instead)
- update README and vim help accordingly
- gw is already taken (see :help gw), maybe use ggb instead?
- test it with typedef, packed/unpacked types etc
OK. How about this way. I don't know vim script itself. So please let me know how can I add wire option in *.vim files. (I need this to test the code in local computer.)
I will start to modify verilog_instance.py to support wire declaration with the assumption that there could be argv[2]. If argv[2] ==1, wire declaration., else port mapping.
"ggb" is OK to me.
After that, we can discuss the details about README and help.
I finished the merge (removing verilog_wire.py), But it always calls wire declaration. Can you help me what's wrong? This is the main change let cmd = lnum1 . "," . lnum2 . "!" . " " . s:plugin_dir_path . "/verilog_instance.py " . g:verilog_instance_skip_last_coma . " " . s:verilog_instance_wire_declaration
if !hasmapto('<Plug>VerilogInstance') && maparg('gb','n') ==# '' let s:verilog_instance_wire_declaration = 0 xmap gb <Plug>VerilogInstance nmap gb <Plug>VerilogInstance nmap gbb <Plug>VerilogInstanceLine endif
if !hasmapto('<Plug>VerilogWire') && maparg('ggb','n') ==# '' let s:verilog_instance_wire_declaration = 1 xmap ggb <Plug>VerilogInstance nmap ggb <Plug>VerilogInstance nmap ggbb <Plug>VerilogInstanceLine endif
@KyleJeong , I will take a look at it in a few days, don't be surprised if my responses are delayed. Thanks!
Oops, sorry, i completely forgot about this PR. Will take a look at it shortly