Kartik Prabhu
Kartik Prabhu
In my case, I first connect to the host with a password, and then I am prompted with two-factor authentication, which requires keyboard-interactive authentication. Currently, the window times out after...
The filepaths for the `include in the Verilog model have typos. For example, [sky130_fd_io__top_gpiov2.v:36]https://github.com/google/skywater-pdk-libs-sky130_fd_io/blob/main/cells/top_gpiov2/sky130_fd_io__top_gpiov2.v#L36) tries to include "sky130_fd_io__top_gpiov2.pp.functional.v", but the file in the directory is called "sky130_fd_io__top_gpiov2.functional.pp.v". The same is...
bit-width difference between I/W and O. bit-width difference between partial sum and final output.
(Make a Memory Pool which lists all possible memory candidates inside. [With different size & same size but different width/deep ratio])
(It right now assumes that data are ready whenever they are needed. But in some memory-bottleneck cases, memory stall could happen and HW utilization rate drops.)
(e.g. Let some operands skip certain level of memory if there is no data reuse possibility.) (e.g. Ping-pong buffer optimization. [what Francky mentioned last time])
(For I/W: stationary/ broadcast/ unicast/ systolic) (For O: stationary/ adder tree/ systolic) (Register shared by a group of PEs) (Multi-dimensional PE cluster support [like the 3D computing kernel from Huawei,...