Jim Lewis

@Paebbels the path issue should be able to be addressed. I think activehdl needs absolute paths, but Siemens relative paths. So if ghdl needs relative paths that is just a...

This turns out to be a complex issue with respect to for loops and driver issues. In the VHDL working group, we have talked about a similar VHDL issue here:...

Generate is a concurrent statement - just like an architecture. So you can have a process inside of the generate statement - and the generate index is still static. From...

@davidgussler Are you looking to do the https://github.com/fpganinja/taxi stuff in VHDL? Be sure to look at PoC (https://github.com/VHDL/PoC) and OpenLogic (https://github.com/open-logic/open-logic) libraries - that said non-duplicated work would be great....

@davidgussler VUnit only provides a minor part of OSVVM's utility library. OSVVM goes well beyond that.

Does ghdl set some kind of exit status due to a program seeing an assert? From an execution perspective, OSVVM tcl is seeing a exit code of 1 for some...

@kev-cam This sort of proposal is appropriate for the IEEE VHDL working group. Please post them here: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/ It is not because we are not listening to you. The IEEE...

@kev-cam There is no reason you cannot define two different versions of a context declaration, one that includes library ieee and package std_logic_1164 and one that includes library kev and...

I should note that FPGAs do not have internal bidirectional drivers - and ASICs rarely use internal bidirectional drivers - so drive strength is irrelevant internally. It is only interesting...

With respect to 'X' pessimism, VHDL has 'X' and '-'. If you follow the notion of assign 'X' when you mean don't care and check against '-' when you mean...