Georgi Mirazchiyski

Refactors the device config parsing by making it agnostic of the way the SYCL device is targeted, either by passing a device triple plus arch special string to `-fsycl-targets` or...

The AMDGPU backend supports sequential consistency ordering semantics for all atomics correctly and implements for all relevant architectures since GCN.

[SYCL][AMDGPU] Add flag to enable cross-address space syncscopes for atomics on AMD

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TODO: Add description.

(This is currently a WIP) TODO: Add description and explanation of the changes in this refactor. **TODO:** Revisit this making a simpler helper `getUSMHostOrDevicePtr` function internal to `enqueue.cpp`, turning the...

[CUDA][HIP] Catch and report bad_alloc errors for event object creation

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This PR is just to make sure there errors are reported accordingly if new fails to allocate the requested space when creating UR event object from a native event. inte/llvm...

[CUDA] Use appropriate return code for out of registers kernel launch

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This PR changes the returned error code for exiting the kernel launch entry point in CUDA when exceeding the maximum available registers for execution on the SM. Previously we were...

[HIP] Enable more ordering and scope capabilities for atomic memory ops

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DPCPP changes: - https://github.com/intel/llvm/pull/12938 (enables `sycl::memory_order::seq_cst` in `sycl::atomic_ref`)

DPCPP - some fence libclc refator plus CI testing: - https://github.com/intel/llvm/pull/12872

[CUDA][HIP] Return error on silently failing urEventGetInfo queries for interop created events

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This PR addresses https://github.com/oneapi-src/unified-runtime/issues/1235 by returning an error on event queries, specifically `UR_EVENT_INFO_COMMAND_QUEUE`, that cannot be supported for the CUDA and HIP adapters. This is an effect of creating the...