Liam Gallagher

Cover is not yet implemented for Chiseltest

3

Cover statements are not yet possible. Something like: ```scala class Foo() extends Module { val out = IO(Output(Bool())) val i = Counter(10) out := i === 9 cover(out) } ```...

Implement SytemVerilog style Sequences

1

SystemVerilog's sequence construct seems very useful. It might not be useful to entirely copy the syntax but I'd like to capture it's powerful semantics. Perhaps it would be sufficient to...