Implement SytemVerilog style Sequences

[Gallagator]

SystemVerilog's sequence construct seems very useful. It might not be useful to entirely copy the syntax but I'd like to capture it's powerful semantics. Perhaps it would be sufficient to take in a predicate and a Seq of sequence objects. For example:

sequence(start, Seq(Once(a), AtLeast(b, 3), DontCare(10), done))

Translating to a sequence like the folowing:

start |-> a ## b[*3:$] ## true[*0:10] ## done

In turn, this could return a signal which represents the sequence and can be asserted. But really I don't know if this is a good direction to move in and this is just off the top of my head with little deep understanding of sequences. I'm mostly making this Issue to get a better idea of what can be done.