Jiaxun Yang
Jiaxun Yang
I’m excited to share that our project has just hit its 5-year milestone! As part of our ongoing development, I'm planning to release v1.0.0 soon, which will include significant improvements...
``` 2024-11-01 14:35:17.502 Lightning automatically upgraded your loaded checkpoint from v1.5.4 to v2.3.3. To apply the upgrade to your files permanently, run `python -m pytorch_lightning.utilities.upgrade_checkpoint ../root/.cache/torch/whisperx-vad-segmentation.bin` 2024-11-01 14:35:17.506 Created a...
Seems not necessary with ACPI enabled OS at the moment. But we should try to extract information from ACPI to construct MPTable and PIRQ table to serve some legacy OS.
The universal goal is to make those actions available in forks, remove some cumbersome scripts and unnecessary steps, enable arm64 build and upload to ghcr.io as an alternative container registry....
Improve up GitHub action by bumping software versions, use cache to preserve tool builds, and use Clang to speed up verilator.
Currently, SeaBIOS booting priority is based on PCI scan sequence. We should at least set the device containing `csmwrap.efi` file to be first boot option. Pass it via BBS table.
Hi everyone, I've just enabled the GitHub [wiki](https://github.com/FlyGoat/csmwrap/wiki) for documentation and created initial subpages for OS and Platforms. We also need comprehensive use guides to help users get started. Since...
Some platforms have issue on accessing PCI config space via 0xcf8 & 0xcfc IO ports, we should parse `MCFG` and use ECAM to access PCI config space whenever possible. This...
Implement CBFS to pass sideband information to SeaBIOS, to avoid being too intrusive to SeaBIOScode. Since we are already using coreboot tables to pass framebuffer information, we just need to...
As reported by @mintsuki, some Intel Arrow Lake S systems have multiple root buses (i.e 0x00-0x7F, 0x80-0xFF). SeaBIOS need appropriate hint to probe multiple root buses (romfile `"etc/extra-pci-roots"`). My current...