Finn Wilkinson

RE MRS and NZCV, I'm not aware of any MRS instruction that sets the NZCV and I couldn't find [anything in the spec](https://developer.arm.com/documentation/ddi0602/2024-06/Base-Instructions/MRS--Move-System-register-to-general-purpose-register-?lang=en) either... For `casal` I was unaware that...

To add (another) bug to the above to add to the todo list for post-Alpha, `AArch64_ADD_ZI_B` type instructions have the imm set weirdly (example bytecode `00c12025`: ```bash 0 cb 3e...

Just to add, the above is seen with other similar instructions too (i.e. `AArch64_AND_ZI`, example bytecode `00068005`)

Sorry - I have just checked the spec and the current implementation is correct.... Apologies for any confusion!!! https://developer.arm.com/documentation/ddi0602/2024-09/SVE-Instructions/AND--immediate---Bitwise-AND-with-immediate--unpredicated--?lang=en

Hi, please could you try running this on our `dev` branch? I suspect that the compiler you are using has generated an instruction we do not have execution logic for...

Hi, thanks for raising this issue. The `ldrsb` is supported by SimEng, however the execution logic is currently not present on the branch you are using for this specific version...

I'm glad to hear the new branch works for your previous issue! The issue that you are (repeatedly) running into is the simulator trying to execute and instruction, but there...

Hi, It looks like you are doing the right process, but as you said the `paciasp` instruction is not supported yet. Using GCC/G++ 10.3 should help this, or you could...

Hi, Regarding workflow it is definately easiest to do on a Linux machine as cross compilation with LLVM is usually very simple out of the box. But most of our...

Could you also add tage to the a64fx_SME.yaml config