UoB-HPC
Issue with ldrsb Instruction Exception
Check List
- [√ ] The binary I am trying to run has been compiled statically for either RV64 or AArch64.
- [ √] The compiled binary is a Linux Elf file.
- [ √] I have provided both a config file and a binary to SimEng as runtime arguments.
Binary File Information
Please run file on the binary used and paste the output below (i.e. file myBinary.elf).
test: ELF 64-bit LSB executable, ARM aarch64, version 1 (GNU/Linux), statically linked, for GNU/Linux 3.7.0, with debug_info, not stripped
System Description Please provide the following as a list:
- The Operating System of the system you are running SimEng on Ubuntu20.04
- The compiler used to compile SimEng and its version clang version 19.1.3
- The compiler used to compile the static binary and its version gcc13.2 from https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads/13-2-rel1
- The ISA or specific processor that the binary was compiled for -march=armv9.2-a -mcpu=neoverse-v1+sme2
- The processor of the system you are running SimEng on A64FX_SME
- The main memory capacity of the system you are running SimEng on
SimEng Version Provide the SimEng repository branch, commit hash, and version tag (if relevant) that the issue is present on. 7af3bc3fe7deb703756def31a208839bc5bdc4c2
SimEng CMAKE Options Used
Provide a bullet list of all CMAKE options used. E.g. -DCMAKE_BUILD_TYPE=Release.
-DCMAKE_BUILD_TYPE=Release
Binary Compilation Instructions Provide a bullet list of how the binary in question was compiled, including all compiler flags used. compiler flags: -march=armv9.2-a -mcpu=neoverse-v1+sme2
SimEng Command Line Expression
Provide the command line expression used to run SimEng e.g. ./simeng /path/to/configs/a64fx.yaml /path/to/myBinary.elf
SimEng Metadata Output If your simulation begins to execute the binary, please provide the metadata that SimEng prints at the start of execution. E.g.
[SimEng] Build metadata:
[SimEng] Version: 0.9.6
[SimEng] Compile Time - Date: 21:03:58 - Sep 28 2024
[SimEng] Build type: {Release}
[SimEng] Compile options: $<$<COMPILE_LANGUAGE:CXX>:-fno-rtti>;-Wall;-pedantic;-Werror
[SimEng] Test suite: {OFF}
[SimEng] Running in Out-of-Order mode
[SimEng] Workload: /home/lin/workspace/sme_test/test
[SimEng] Config file: a64fx_SME.yaml
[SimEng] ISA: AArch64
[SimEng] Auto-generated Special File directory: True
[SimEng] Special File directory used: /home/lin/workspace/SimEng/build/specialFiles/
[SimEng] Number of Cores: 1
[SimEng] Starting...
[SimEng:ExceptionHandler] Encountered execution not-yet-implemented exception
[SimEng:ExceptionHandler] Generated by instruction:
[SimEng:ExceptionHandler] 0x000000000044eadc: 41 14 c0 38 ldrsb w1, [x2], #1
[SimEng:ExceptionHandler] opcode ID: 3406
[SimEng:Core] Halting due to fatal exception
[SimEng] branch.executed: 1615
[SimEng] branch.mispredict: 581
[SimEng] branch.missrate: 36%
[SimEng] cycles: 7015
[SimEng] decode.earlyFlushes: 0
[SimEng] dispatch.rsStalls: 1004
[SimEng] fetch.branchStalls: 2075
[SimEng] flushes: 553
[SimEng] ipc: 0.74
[SimEng] issue.backendStalls: 462
[SimEng] issue.frontendStalls: 1279
[SimEng] issue.portBusyStalls: 62
[SimEng] lsq.loadViolations: 22
[SimEng] rename.allocationStalls: 5
[SimEng] rename.lqStalls: 0
[SimEng] rename.robStalls: 0
[SimEng] rename.sqStalls: 0
[SimEng] retired: 5194
Problem Description Does SimEng not support the LDRSB instruction?
Hi, thanks for raising this issue. The ldrsb is supported by SimEng, however the execution logic is currently not present on the branch you are using for this specific version of the instruction.
Given you are using GCC 13.2 to compile your binary, and you are targetting SME2, can you try and use the sme-loops-support branch instead? This has a) SME2 support (in beta) and b) much better instruction support for newer compiler versions.
Let me know how you get on - any other issues / if this issue still persists then please update this issue
**memory-paper ** commented Nov 19, 2024
Thank you for your solution. After following your suggestion to switch to the sme-loops-support branch and trying again, I found that the previous issue is no longer occurring. However, a new issue has emerged, and the details are as follows:
[SimEng] Build metadata:
[SimEng] Version: 0.9.6
[SimEng] Compile Time - Date: 16:31:43 - Nov 20 2024
[SimEng] Build type: Release
[SimEng] Compile options: $<$<COMPILE_LANGUAGE:CXX>:-fno-rtti>;-Wall;-pedantic;-Werror
[SimEng] Test suite: ON
[SimEng] Running in Out-of-Order mode
[SimEng] Workload: /home/lin/workspace/sme_test/gemm_micro_64_16_2/test
[SimEng] Config file: /home/lin/workspace/SimEng/configs/a64fx_SME.yaml
[SimEng] ISA: AArch64
[SimEng] Auto-generated Special File directory: True
[SimEng] Special File directory used: /home/lin/workspace/SimEng/build/specialFiles/
[SimEng] Number of Cores: 1
[SimEng] Starting...
[SimEng:ExceptionHandler] Encountered execution not-yet-implemented exception
[SimEng:ExceptionHandler] Generated by instruction:
[SimEng:ExceptionHandler] 0x0000000000400df4: 80 00 20 e1 str za[w12, 0], [x4]
[SimEng:ExceptionHandler] opcode ID: 6858
[SimEng:ExceptionHandler] Extra information: This instruction is an alias. The printed mnemonic and operand string may differ from the underlying opcode.
[SimEng:Core] Halting due to fatal exception
[SimEng] branch.fetched: 118611
[SimEng] branch.mispredicted: 4826
[SimEng] branch.missrate: 11.4%
[SimEng] branch.retired: 42465
[SimEng] cycles: 489535
[SimEng] decode.earlyFlushes: 0
[SimEng] dispatch.rsStalls: 117606
[SimEng] fetch.branchStalls: 68670
[SimEng] flushes: 20309
[SimEng] ipc: 0.63
[SimEng] issue.backendStalls: 39256
[SimEng] issue.frontendStalls: 51137
[SimEng] issue.portBusyStalls: 11197
[SimEng] lsq.loadViolations: 15306
[SimEng] rename.allocationStalls: 24654
[SimEng] rename.lqStalls: 0
[SimEng] rename.robStalls: 3
[SimEng] rename.sqStalls: 0
[SimEng] retired: 309010
[SimEng] Finished 489535 ticks in 686ms (714 kHz, 0.45 MIPS)
I hope this information can help diagnose the new issue. Thanks again!
I'm glad to hear the new branch works for your previous issue!
The issue that you are (repeatedly) running into is the simulator trying to execute and instruction, but there is no execution logic present for this instruction. For SME codes in particular, this is likely to be common due to SimEng only recently adding full SME and SME2 support in any capacity.
In our documentation (found here, and likely lacking some SME-specific information) you can find details on how to add new execution logic into SimEng. SME instructions are slightly more complicated due to the instructions being more complex than a base ISA instruction, but there are plenty of SME instructions already implemented (including loads and stores) in this new branch that you can use as guidance. All SME instructions have a // SME comment inside the execution logic so that they can be identified easily.
In short: you should only need to edit the following two files to add execution logic:
src/lib/arch/aarch64/Instruction_execute.ccsrc/lib/arch/aarch64/Instruction_address.cc(load and store instructions only)
You can also find the exact ENUM value of the instruction that requires execution logic by searching for the opcode ID printed by [SimEng:ExceptionHandler] in the build/_deps/capstone-lib-src/arch/AArch64/AArch64GenInstrInfo.inc file (in your above case, this will be ID 6858). It can also be helpful to add tests for new instructions to ensure they are working correctly. This should be done in the relevant file in the test/regression/aarch64/instruction directory.
I hope this helps, let me know if you get stuck or need more guidance.
I'm glad to hear the new branch works for your previous issue!
The issue that you are (repeatedly) running into is the simulator trying to execute and instruction, but there is no execution logic present for this instruction. For SME codes in particular, this is likely to be common due to SimEng only recently adding full SME and SME2 support in any capacity.
In our documentation (found here, and likely lacking some SME-specific information) you can find details on how to add new execution logic into SimEng. SME instructions are slightly more complicated due to the instructions being more complex than a base ISA instruction, but there are plenty of SME instructions already implemented (including loads and stores) in this new branch that you can use as guidance. All SME instructions have a
// SMEcomment inside the execution logic so that they can be identified easily.In short: you should only need to edit the following two files to add execution logic:
src/lib/arch/aarch64/Instruction_execute.ccsrc/lib/arch/aarch64/Instruction_address.cc(load and store instructions only)You can also find the exact ENUM value of the instruction that requires execution logic by searching for the
opcode IDprinted by[SimEng:ExceptionHandler]in thebuild/_deps/capstone-lib-src/arch/AArch64/AArch64GenInstrInfo.incfile (in your above case, this will be ID6858). It can also be helpful to add tests for new instructions to ensure they are working correctly. This should be done in the relevant file in thetest/regression/aarch64/instructiondirectory.I hope this helps, let me know if you get stuck or need more guidance.
Thank you for your valuable suggestion! I will try the approach you recommended to see if it resolves the issue I’m facing. I really appreciate your help and the time you took to provide a solution!