Finn Wilkinson

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Looking into this a bit further, it seems to originate from the `AArch64GenCSMappingInsnOp.inc` file where all SME based instructions with an index have `CS_OP_MEM`. In capstone's LLVM, `llvm/utils/TableGen/PrinterCapstone.cpp` the function...

I'm not 100% sure on how to implement a fix for this, but for the regex above; all AArch64 memory operands will be preceeded by `, ` (i.e. `, [x6]`)...

Great, thank you for the update!

Hi @Rot127 , sorry for the delayed reply I've only just seen the newest comments. This generallt all looks good to me, but I have some concerns about predicates in...

I think the current implementation of SME operands (non predicates) works well, so I'd be opposed to changing from this. How about having a new `aarch64_op_pred` type for all predicates...

Will `aarch64_op_index` be used for anything else? If not couldn't we just do ```C typedef struct aarch64_op_pred { aarch64_reg pred; aarch64_reg vec_select; int32_t im_offset; } aarch64_op_pred; ``` ? And for...

> But let's just hope ARM will not introduce more extensions with this index pattern. Yes, lets! Here are some more complex assembly tests that would be good to validate...

> Change is done. Also fixed, that the predicate regs were not added to the register written list. I think this looks great now. Thanks! > Sorry, late night working....

I've also just noticed that `SMSTART` currently has `Registers modified: nzcv` which is false (as far as I can tell from the spec). Only `PSTATE` is updated. Similar is true...