Peter Lebbing

> The behavior of full/empty signals in the Haskell model is not tested. What do you mean? It's [in the test bench](https://github.com/clash-lang/clash-compiler/pull/2270/files#diff-3e45d27283741d1780f33faf06b95c6578c6140bfe30165fdd756efcd84f209bR63-R79), right? I have to admit those are only...

Note that our asynchronous RAMs also only have undefined initial contents. It could be worthwhile to add it there as well.

I am so curious to figure this out! What the...!

I think you've made a mistake, Christiaan. `Eq` is tree-based, but the issue is about `Ord` (just below in the code, actually). That's expressed in `foldr`, although I'm hoping that...

I think it's better if it has its own PR, but I don't have a strong position on this. Note that adding the `HasCallStack` contraint means renumbering all bloody `~ARG`s...

> Worth mentioning that this setting the exit code is something simulator-specific still. And if anyone knows how to do that in Vivado, I'm all ears! If you also know...

Note that changing the `c$` prefix doesn't help; if you use an implicit clock, the argument is named like `$d(%,%)` which maps to the basic Verilog identifier `_$d_0` exhibiting the...

Here's a small reproducer ```haskell module ImplClock where ​ import Clash.Prelude ​ topEntity :: HiddenClock System => Signal System (Unsigned 8) -> Signal System (Unsigned 8) topEntity = dflipflop {-#...

Ah it might be the clock crossing picking a different order; there's probably two concurrent processes where it is undefined which runs first. So far all simulators picked the same...

> I hit this issue on `Bit` just yesterday, I think `Bit` behaving this way is very surprising. I can understand why it's like this for `BitVector` because some bits...