CarrolXC

--top-module 'sim' was not found in the design

5

I used the gen.py file to generate a litedram core, and meanwhile a build_xxxx.sh was generated as well. When I tried to run build_xxx.sh file , it point to a...

Corresponding verilog testbench for ASIC

1

Hi, I generated a verilog module for the litedram core and now I want to simulate it as as ASIC design, basically I am trying to dummy out those interfaces...

submodules verilog

2

Hi , I am generating verilog file through gen.py and I did see a top level verilog file in the "build" folder. However , I found I missed all the...