CarrolXC

What I was trying to do is simulating the entire memory subsystem and it seems like what I generated contains all the modules(not 100% sure). So the rest requirement might...

@enjoy-digital Thanks for your explanation and suggestions! That's helpful. I was able to call the /litedram/build/sim/gateware/sim.v by running /litedram/build/sim/gateware/run_sim.sh and find some memory-related results print in the terminal, it seems...

@dinaabdelbaky Hi Dina, Actually I don't have enough ideas on your question but I am trying to share my feeling. Q1.The core you generated from gen.py should be a self-contained...