Bruno Levy

So it is probably something that I'm doing in `riscv_assembly.v` that works with Yosys, with Verilator and with Icarus but that does not work with Vivado. I'll take a look...

I'm currently writing a small test program to try to figure out what happens with Vivado, will keep you updated.

Pushed `step7_with_disasm.v`, to test whether my risc-V assembler in VERILOG works with VIVADO. Here is what it displays under Icarus and Verilator. Would you tell me whether you get the...

Thank you for testing ! (pushed the fixes) From the output: the assembler and disassembler both work, so we still don't know who is the culprit ! Where do you...

I pushed a new version of `step7_with_disasm.v`, that displays the current instruction being executed in BENCH mode. Here is what it displays under Icarus and Verilator. What does it give...

So I suspect simulation does not simulate the clock (which would explain why nothing happens). Was it working with steps 1-6 ?

Hi, Nice job ! It is interesting to see these block diagrams. Here is some feedback/suggestions that comes to my mind (but I'm unsure, I may be wrong, this needs...

It really looks like mismatched BAUD rate but can be something else: by default, I have configured it to run at 1000000 (1 million) bauds. Some hw/OS combinations may not...

It is because you need to wait for `uart_busy` to be deasserted before sending the next character (your state machine is much much faster than the UART).

Hi Farnik, The `Warpdrive` plugin (note: different from the `warpdrive` program that you are using for astrophys) depends on the `exploragram` optional library in `geogram`. See instructions [here](https://github.com/BrunoLevy/geogram/wiki/compiling_MacOS#additional-information) on how...