Asma-Mohsin
Asma-Mohsin
i think you should first write powered verilog of this synthesis file cause currently your cells have no power and ground connections. thus going on unknown state.
Hey @kareefardi Thankyou for taking the time to look into it. We figured out what was causing the issue. So actually we have blockRAM macro in our design. We have...
Not exactly sure what do you mean by min area rule in this context. The issue is that the pdk has some vias in which metal enclosure is not sufficient...