Netlist Simulation Issues: Unknown Values/Syntax Errors

[deepsita]

The simulation of synthesized netlist is always XXX. as shown in the image.

However, the Synthesis is shown successful as shown in the below image of terminal

The procedure to reproduce the same is given in the https://github.com/deepsita/mythcore_synth git clone https://github.com/deepsita/mythcore_synth.git cd mythcore_synth/post synth Simulation/ iverilog gls.v mythcore.synth.v primitives.v sky130_fd_sc_hd.v ./a.out gtkwave gls.vcd

[Manarabdelaty]

@deepsita I believe the behavioral models are buggy in the original PDK (see https://github.com/google/skywater-pdk/issues/310) . However, you can simulate with the functional models by passing the FUNCTIONAL define to iverilog (you also need to set UNIT_DELAY macro to some value) : iverilog -DFUNCTIONAL -DUNIT_DELAY=#1 gls.v mythcore.synth.v primitives.v sky130_fd_sc_hd.v

[deepsita]

I tried doing the same, and the following errors are shown. There was a syntax error in 74584 line of the sky130_fd_sc_hd.v, the cell at this line is oai, and the screenshot of the same is also attached.

[Manarabdelaty]

@deepsita See issues (https://github.com/google/skywater-pdk/issues/298, https://github.com/google/skywater-pdk/issues/297), The current solution (until they are addressed in the skywater-pdk repo) is to manually comment out the wire 1; statement and correct endif SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V to endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V

[donn]

For posterity's sake: the wire 1 issue has been long fixed, but the `endif most definitely has not.

[Asma-Mohsin]

i think you should first write powered verilog of this synthesis file cause currently your cells have no power and ground connections. thus going on unknown state.