AndrewD
AndrewD
For reference the nuttx liteeth driver also had a similar pattern and very low performance. We (@g2gps) made some similar changes and got a big improvement but I'm not sure...
Adding dma capability to liteeth would be ideal, maybe something similar to litesdcard using litedma. This is something we have discussed internally and with @enjoy-digital . We could provide some...
@enjoy-digital @trabucayre see above for a proposal to discuss.
This only affects the way csr longer than 32bits work. Currently those csr are ordered big endian on little endian (by default) CPUs like riscv. For example: - add a...
> updated/rebased/squashed this PR [here](https://github.com/trabucayre/litex/commit/c63e747d3f78fc5f00b2764dc5a5b8e41aabb325). Thanks! I looked at rebasing this yesterday but decided to leave it until later due to the conflicts.
Also note that by default this has no effect on the generated gateware, but it will be require driver changes if the csr_ordering is changed. I have a separate change...
See comment on #1935, but you should be getting a vcd file you can view in gtkwave. Look at the main bus address and data to see what your code...
You could use litescope to capture the soc bus address to see where your code is going. But if you use the sim as per your other issue you are...
`MEMORY { rom : ORIGIN = 0x00000000, LENGTH = 0x00008000 sram : ORIGIN = 0x10000000, LENGTH = 0x00002000 main_ram : ORIGIN = 0x40000000, LENGTH = 0x00004000 bootrom : ORIGIN =...
You can interact with the bios, or a running firmware, via the terminal when running the simulator.