AndrewD

Not that sda is driven open drain, so it's high impedance when sda = 1. I don't actually see the need for oe at all. Also note that there is...

See #2022 for the python usage of the simple core. Also #2026 has a very interesting i2c core that looks very promising.

> Are you sure SDA will be Open drain on any FPGA? So far ive only seen Tristate output support. It implements open drain-like "emulation" with tristate gpio. The other...

In the target you need to use add_slave() to connect the i2c memory mapped interface to the soc. I'll aim to post an example tomorrow.

Something like the below will be close: ``` self.bus.add_slave(name="i2c", slave=self.i2c.bus, region=SoCRegion( origin = 0xe000_0000, size = 0x1000, )) ```

This is a complete example integration: ``` from litex.soc.cores.i2c import I2CMaster self.i2c = I2CMaster(platform.request("i2c", 0)) self.bus.add_slave( name="i2c", slave=self.i2c.bus, region=SoCRegion( origin=0x8000_0000, size=8, cached=False, ), ) self.irq.add(name, use_loc_if_exists=True) ``` Now in csr.csv...

Description edited, more to do

@enjoy-digital @trabucayre this issue describes the motivation behind the changes in #1975. This is a minimal change to start dynamically generating dts content for litex cores/modules instead of hard coding...

Thanks for the confirmation and link: my focus has been on other docs.

If throwing an exception is the existing pattern then following this for Efinix would be sufficient for now - openfpgaloader just returning a non-zero value on error is all we...