Alan-19950616

I want to add a verilator-generated uart model to systemc project, but there's a problem.

2

I'm not sure if it's a systemc problem or a verilator problem. Error message ``` Warning: (W116) channel doesn't have a default event In file: /home/nuclei/FastModel/systemc-2.3.4/src/sysc/communication/sc_interface.cpp:54 pure virtual method called...

OpenOCD return error when using GDB to hit hardware breakpoints on hardware that doesn't support them.

10

I think it's better to report a warning when this behaviour is detected than to report an error outright. reporting an error will cause GDB to disconnect https://github.com/riscv-collab/riscv-openocd/blob/cb2b3945143efda7196d14ae60c9877c289026a7/src/server/gdb_server.c#L1832

In the `riscv_run_algorithm` function, the single_hart parameter of `riscv_resume` is true. then at `old_or_new_riscv_poll` since both the `halted` and `running` variables are not equal to 0, then a call to...

Run NocTestAXI403 Fail

9

# Command > CONSTELLATION_STANDALONE=1 sbt "testOnly constellation.NoCTestAXI403" # Error Info ``` Constellation: AXI4NoC Starting NoC RTL generation Constellation: AXI4NoC Finished NoC RTL generation [info] constellation.NoCTestAXI403 *** ABORTED *** [info] java.lang.OutOfMemoryError:...

Using the `info reg all` command within gdb returns an `remote failure reply 'E0E'`

10

These error messages cause the IDE register component to not display properly. https://github.com/riscv-collab/riscv-openocd/commit/236c54c94a53ff76537a1bf91cfe74a264a2756f This is part of the gdb output: ``` (gdb) info reg all ...... fflags 0x0 RD:0 NV:0...

### Description An unexpected error occurred in the renderer process. ### Stack Trace ``` TypeError: Cannot read properties of null (reading 'querySelector') at Ao (file:///C:/Program%20Files/MarkText/resources/app.asar/dist/electron/renderer.js:2:155286) at Ao (file:///C:/Program%20Files/MarkText/resources/app.asar/dist/electron/renderer.js:2:155491) at r...

Single-core running “target_run_algorithm” in SMP architecture forcibly interrupted by ”riscv_openocd_poll“

13

The run algorithm code segment. https://github.com/riscv-collab/riscv-openocd/blob/riscv/src/target/riscv/riscv.c#L3482-L3521 The problematic code segment. https://github.com/riscv-collab/riscv-openocd/blob/riscv/src/target/riscv/riscv.c#L3926-L3929

Error reading registers due to “-rtos hwthread” parameter of “target create”

4

- Test 1 openocd.cfg ``` set _CHIPNAME0 riscv0 jtag newtap $_CHIPNAME0 cpu -irlen 5 -expected-id 0x10900a6d set _TARGETNAME0 $_CHIPNAME0.cpu target create $_TARGETNAME0.0 riscv -chain-position $_TARGETNAME0 -rtos hwthread target create $_TARGETNAME0.1...

I get an error when calling the dm_write befor init

17

openocd.cfg ``` ...... riscv set_mem_access sysbus riscv dm_write 0x38 0x40000 riscv dm_write 0x39 0x80000000 riscv dm_write 0x3c 0x1234 init ...... ``` The error log ``` Error: [riscv0.cpu] dmi_write is not...