I want to add a verilator-generated uart model to systemc project, but there's a problem.

[Alan-19950616]

I'm not sure if it's a systemc problem or a verilator problem.

Error message

Warning: (W116) channel doesn't have a default event
In file: /home/nuclei/FastModel/systemc-2.3.4/src/sysc/communication/sc_interface.cpp:54
pure virtual method called
terminate called without an active exception

For details, click on this link https://github.com/mariusmm/RISC-V-TLM/discussions/24

[maehne]

Even though the error is signalled in a file belonging to the SystemC PoC implementation, the problem lies more likely in your model. I suspect that your model is using some custom channel, which does not fully overload some pure virtual member function of the inherited base class. Use the appropriate SystemC forum to ask for support once you have ideally a minimal self-contained reproducer of the problem, which can be easily checked by the forum members.

[Alan-19950616]

Thanks for the reply, I'm in active communication with verilator. Let me know if you find anything afterward.

https://github.com/verilator/verilator/issues/4434