tree-sitter-verilog
tree-sitter-verilog copied to clipboard
tree-sitter
SystemVerilog grammar for tree-sitter
Given this: ```verilog module top; wire a[1:0][1:0]; assign a[1][0] = 0; endmodule; ``` Run tree-sitter like this: ``` tree-sitter parse top.v ``` Got this error: ``` top.v 0 ms (ERROR...
This library has not yet been published to crate.io. Can we publish it? btw. the repository part in Cargo.toml is wrong. Could it be caused by this bug?
Given this: ```verilog task automatic t1; input a; output b; begin a = b; end endtask module top; wire i, j; always @(*) begin t1(i, j); end endmodule ``` Run...
Hi, Our organization is interested in incorporating this tool (we need a tree-sitter systemverilog implementation), but it would really be an easier process (for us and everyone), if it could...
Hi, For positional instantiation, seems the first port will always be output and others will be input? 
Testing a json parser that do not manage utf-8 characters I found that this grammar has some that I'm not sure it's intentional: ``` "value": "–>" ///verilog "value": "->" ///cpp...
I find that it doesn't support fold on instantiated instances，and port declaration, is it possible to support that? Thanks, Alex
I noticed that system tasks ($display(), $cast(), ...) are not highlighted by treesitter. Will it be implemented?
Please also see https://github.com/nvim-treesitter/nvim-treesitter/issues/6616. The following code fails to properly parse: ```sv module test(); generate for (unit = 0; unit < `UNITS; unit += 1) begin always_ff @(posedge clk) begin...
simple example ``` ============================================ always -- case member ============================================ module abc (); always_comb case ( foo ) 8'h00, 8'h05: bar.baz = 1'b0; default bar = 1; endcase endmodule ---- ```...
