tree-sitter-verilog
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blocking assigment with member_identifier miss parse to clockvar_expression
simple example
============================================
always -- case member
============================================
module abc ();
always_comb
case ( foo )
8'h00, 8'h05: bar.baz = 1'b0;
default bar = 1;
endcase
endmodule
----
parse to
(source_file
(module_declaration
(module_header
(module_keyword)
(simple_identifier))
(module_nonansi_header
(list_of_ports))
(module_or_generate_item
(always_construct
(always_keyword)
(statement
(statement_item
(case_statement
(case_keyword)
(case_expression
(expression
(primary
(simple_identifier))))
(ERROR
(case_item_expression
(expression
(primary
(primary_literal
(integral_number
(hex_number))))))
(case_item_expression
(expression
(primary
(primary_literal
(integral_number
(hex_number))))))
(clockvar_expression
(clockvar
(simple_identifier))
(select1
(member_identifier
(simple_identifier)))))
(case_item
(statement_or_null
(statement
(statement_item
(blocking_assignment
(operator_assignment
(variable_lvalue
(simple_identifier))
(assignment_operator)
(expression
(primary
(primary_literal
(integral_number
(decimal_number
(unsigned_number)))))))))))))))))))
maybe correct parse is
(source_file
(module_declaration
(module_header
(module_keyword)
(simple_identifier))
(module_nonansi_header
(list_of_ports))
(module_or_generate_item
(always_construct
(always_keyword)
(statement
(statement_item
(case_statement
(case_keyword)
(case_expression
(expression
(primary
(simple_identifier))))
(case_item
(case_item_expression
(expression
(primary
(primary_literal
(integral_number
(hex_number))))))
(case_item_expression
(expression
(primary
(primary_literal
(integral_number
(hex_number))))))
(statement_or_null
(statement
(statement_item
(blocking_assignment
(operator_assignment
(variable_lvalue
(simple_identifier)
(select1
(member_identifier
(simple_identifier))))
(assignment_operator)
(expression
(primary
(primary_literal
(integral_number
(binary_number)))))))))))
(case_item
(statement_or_null
(statement
(statement_item
(blocking_assignment
(operator_assignment
(variable_lvalue
(simple_identifier))
(assignment_operator)
(expression
(primary
(primary_literal
(integral_number
(decimal_number
(unsigned_number)))))))))))))))))))
https://github.com/tree-sitter/tree-sitter-verilog/pull/58 when change grammar.js follow this PR
but corpus folder dont have clocking block test pattern. so cant check side effect
@drom could you add test pattern for this commit? if you could https://github.com/tree-sitter/tree-sitter-verilog/commit/fd07bc8b3f67a8b1d8207d02d4dbdcb7dd4371c7