verilator topic

SCARV: a side-channel hardened RISC-V platform

scarv

:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and v...

microdynamics-cpu

A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator...

vmunoz82

Bazel build rules for Verilator

kkiningh

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

sgherbst

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

dpretet

Universal Verification Methodology (UVM) base libraries, with edits for Verilator

verilator

A collection of debugging busses developed and presented at zipcpu.com

ZipCPU

Digital Interpolation Techniques Applied to Digital Signal Processing

ZipCPU

CMod-S6 SoC

ZipCPU