Seth Pellegrino

> Also it's not clear if the hardware takes writes to the SPI_Wx_REGs during a transfer. I ran a small experiment that set up a 128-byte transfer (in quad mode)...

I've been looking into this a bit with @dougli1sqrd , and the panic seems to be limited to this shift operation: https://github.com/esp-rs/esp-hal/blob/7889a992d7efcbbba0a5c7ef679694877f30380e/esp-hal-common/src/interrupt/riscv.rs#L267 I can reliably reproduce an underflow panic while...

Looks like it's ultimately a LLVM bug: https://github.com/llvm/llvm-project/issues/57988 I've got two ideas of varying quality: 1. As mentioned, change the esp32c3 interrupt handler to operate over `u64`s 2. Teach `esp32c3/build.rs`...

Ooh, good call about user code: I'll reworded the message to include some of that flavor and open a PR! Thanks for all your help and encouragement navigating the wild...

Oops, just saw your comment @jessebraham : unless you object, I'll move discussion over to the PR I just opened.

> Regarding disassembling code: You probably already know it but anyways: Passing the option S to objdump annotates the disassembly with the original source code producing the code :open_mouth: I...

Well, also lacking better ideas, I've applied brute force: I reviewed [`spi_new_trans`](https://github.com/espressif/esp-idf/blob/df9310ada26123d8d478bcfa203f874d8c21d654/components/driver/spi/gpspi/spi_master.c#L584-L586) over in the esp-idf by manually flattening all the definitions until I had one big block o' C,...

I appreciate you, thanks for taking the time to read it! I do have fun with this kind of stuff, but it's definitely _more_ fun when the conclusion is a...

You'd written: > The idea behind the #[ram] macro is for the "initial" function that should be placed into ram, after that any functions that might get called inside there,...

Thanks for the suggestion! I took a look through there, and all I could find were ultimately various links to the github release assets, which (at least all the ones...