Seth Pellegrino

I noticed that the links from `riscv.org` also look like they're going straight to the github release assets, too. The [docs](https://docs.github.com/en/rest/releases/assets?apiVersion=2022-11-28#upload-a-release-asset) seem to suggest it ought to be possible, at...

> The [docs](https://docs.github.com/en/rest/releases/assets?apiVersion=2022-11-28#upload-a-release-asset) seem to suggest it ought to be possible, at some level, to control what content type an asset is served with. Just wanted to follow up on...

Hmm, you're right: that minimal example was too minimal, sorry. When I tried it again, I got the same crash in the demo site from the full Dockerfile (which I'm...

Thanks, that's very helpful! I'll see what I can do with your guidance here. FWIW, if someone else happens along and fixes the issue before I get to it, I'd...

Oh, I also meant to mention: I found someone on the mailing list with a similar-looking symptom ( https://groups.google.com/g/chipyard/c/i0pNR4t8HFA/m/NBMP4fcsAQAJ ), but given that they reported 1) the crash occurred in...

I think it depends on how you mean: I noticed the `cur` that's 0x0 in gdb there is a [`static __thread context_t* cur;`](https://github.com/riscv-software-src/riscv-isa-sim/blob/2cfd5393520c0673fd0182fcca430351d9e6682d/fesvr/context.cc#L6); since it's a thread-local, I read that...

Perhaps! I did see that other devices made use of `context_t`, which is what leads me to want to understand the problem a little better. I found certain `--threads` counts...

Hmm, well, yes and no to that last question. Adding a spike tile[^1] did perturb the scheduler enough that the simulation worked at least once[^2] with `VERILATOR_THREADS=3`: ``` [UART] UART0...

Ah, one speculative code change later and, oh, hello: ``` [UART] UART0 is here (stdin/stdout). network init (tid=536361) No tap interface provided network tick (tid=536364) - /home/seth/Code/src/github.com/ucb-bar/chipyard/sims/verilator/generated-src/chipyard.harness.TestHarness.TapNICRocketConfig/gen-collateral/TestDriver.v:158: Verilog $finish ```...

Ok, so I've experimented a bit more, and I've come up with three potentially useful perspectives here: * SimNetwork (& SimBlockDevice) are mis-using `context_t` by stashing the pointer from `context_t::current`...