Greg Davill

I actually wasn't aware that submodules didn't download with a zip version of the repo.. ~Might be easier to store these directly in the repo then... I'd like to ensure...

No worries, thanks!

Looking at the sim output, when adding the cdc elements some critical timing, like async FIFO resets, can take upto 2-3 clocks in the slow domain. Which might require changes...

> Are you running from XIP flash? If so, TinyUSB may be taking too long to respond. This was a common issue in the initial CircuitPython port, which I worked...

Here is my almost working implementation. I still need to bring it upto speed with all the mainline charges: https://github.com/gregdavill/foboot

Initially we can operate the wishbone at 12MHz. Feel free to assign this to me as I've got the OrangeCrab hardware to test on. I'll create a pull request to...

I've got the main code base ported and it's "running" now, some small issues I'm still debugging. - Device does not start with vexriscv "Fomu" variant. Switching to minimal/lite works,...

Clock output using the `USRMCLK` primitive built into `spi_flash.py` is working well. When switching to bit-banging mode the `/WP` and `/HOLD` are tri-stated, my hardware doesn't have any pull-up on...

I think my issue might be the QE bit then... I don't think that is set. So the FLASH is treating IO2/IO3 as HOLD and WP functions.

I'm still trying to understand why the vexriscv core you've configured doesn't like running on my ecp5 platform. The only major change between the up5k and the ecp5 is the...