Greg Davill

I've just tried switching back to the debug build, no difference. It's weird because it works on the up5k Fomu hardware. Which suggests the issue comes from differences between icestorm/trellis....

I've performed a manual bisect of the various VexRiscv options, specifically `--pipelining false` is what's causing the grief. I'm using https://github.com/xobs/VexRiscv-verilog, and running `vexriscv.GenFomu` script If anyone is curious these...

I've got an initial port done. https://github.com/gregdavill/foboot/tree/OrangeCrab I still want to put it through it's paces more, seems a bit fragile to build sometimes. I'm not sure on the best...

@mithro This is the direction I'm thinking of moving. I'd like a way to add some platform specific build commands. For example with ECP5 targets it might be useful to...

Thanks for the examples! That is helpful. I'm refactoring the BaseSoC to add different modules by calling `add_[module]` from the platform. https://github.com/gregdavill/foboot/blob/OrangeCrab/hw/foboot-bitstream.py#L202 I've also added some arg parser options to...

@xobs, what are your thoughts on use of the USB VID:PID for various platforms, or should each platform have their own? I'm specifically wondering if it's beneficial to use different...

I've requested a new code for the OrangeCrab (via pid.codes). I've got the port to an "alpha" state. It's basic functions work. The boot-loader is entered when the button is...

8 bit ``` Info: Logic utilisation before packing: Info: Total LUT4s: 5681/24288 23% Info: logic LUTs: 4529/24288 18% Info: carry LUTs: 630/24288 2% Info: RAM LUTs: 348/12144 2% Info: RAMW...

I setup the `--seed` parameter for the OrangeCrab platform and just let my computer churn away for a bit. I only did 11 runs for each 8/32bit. It's basically all...

Just fixed another bug that was preset in the ECP5 port. I'd misunderstood the logic in `reboot()` so this wasn't working. I've just been cycling the USB port to exit...