arch issues

all: remove redundant type conversion

6

arch/riscv64: Implement RV64G GNU/Plan 9 format disassembler

36

Support all extensions mention in riscv-spec 20191214 Volume 1 Chapter 27: RV32/64G Instruction Set Listings. riscv64spec relies on the riscv-opcodes project: https://github.com/riscv/riscv-opcodes

lrzlin

x86spec: fix header parsing

14

The existing implementation of the Intel x86 doc parser matches headers by just trimming spaces. However, there are cases, when a header string takes several lines, which breaks current switch...

anton-kuklin

arch/x86: Fixed FCLEX/FNCLEX, FCMOVcc, etc... instructions not parse

17

Fixed FCLEX/FNCLEX, FCMOVcc, FPATAN, INVD, INVLPG, LOCK, OUT, OUTS/OUTSB/OUTSW/OUTSD, PUSH, RCL/RCR/ROL/ROR, RDMSR, SAL/SAR/SHL/SHR, SGDT, and SIDT instructions in Intel Instruction Set Reference golang/go#325383-079US, March 2023 is not parse

pdegama

x86: allow decoding of AVX instructions

11

Fixes golang/go#48584 golang/go#41043 golang/go#69792 This PR extends the decoder in x86asm to deal with VEX-encoded instructions, the way I went about this was to extend the table built by x86map...

mhr3