Parser-Verilog
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OpenTimer
A Standalone Structural Verilog Parser
module and_gate ( input a, input b, output out ); assign out = a & b; endmodule
Hi, I am trying to build Parser-Verilog on my ubuntu system. I am getting the following error from `make` command. ``` /usr/bin/cmake -H/home//Parser-Verilog -B/home//Parser-Verilog/build --check-build-system CMakeFiles/Makefile.cmake 0 /usr/bin/cmake -E cmake_progress_start...
If I have this structure, where the escaped name is the last item on the line. wire \n_12 , \n_13 , \n_14 , \n_15 ; I will get: Failed to...
This asks CMake to generate a `compile_commands.json` file so that your IDE (if it uses Language Server Protocol, like VSCode does) can properly syntax-check the files.
Hi, This is not to be merged right now. I tried to make a conan integration, to be able to publish the parser to the [conan center](https://conan.io/center/) but as I...
Hi, Would it be possible to publish the code to conan ? I have tried modifying it to be publishable, but my conan-fu is miserable ...
The ot_parser doesn't support instanciation by position, but it segfaults in this case. Replace the segfault by an error message.
It seems that the parse only support netlist level verilog code? Does it support behavorial level verilog? For example, the `reg` key word seems not supported yet?
PR removes `experimental/filesystem` header file as it is no longer required after #5. The header also causes the following error on MSVC: ``` fatal error C1189: #error: The header providing...
Hi there, I have cloned your repository, and found that the sequence of commands: ```bash git clone https://github.com/OpenTimer/Parser-Verilog.git cd Parser-Verilog mkdir build cd build cmake ../ make ``` Fails to...
