Parser-Verilog
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escaped name that ends at end of line fails
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If I have this structure, where the escaped name is the last item on the line. wire \n_12 , \n_13 , \n_14 , \n_15 ;
I will get:
Failed to match :
Parser error: syntax error, unexpected end of file, expecting NAME or ESCAPED_NAME
The synthesis programs I use sometimes create the above structure.
If the line had the comma at the end, then it reads ok. wire \n_12 , \n_13 , \n_14 , \n_15 ;