Mike Thompson

> We should also try to merge the cva6 dev branch with master soon! Yes, I completely agree. @JeanRochCoulon

(embarrassed cough) Yes, "Steps to Reproduce" _is_ a key part of the issue template that _I_ created, isn't it? Appreciate you keeping me honest. This can be reproduce on the...

Hi @ASintzoff, I forgot to ask, which version of VCS are you using?

Agree with @strichmo that `ifdefs` should be a last resort, but it seems we cannot make progress without them. So I propose that we use them on the [cva6/dev branch...

Wow! I am _so_ glad to see your post on this @Silabs-ArjanB. All of the items you mention have been discussed internally among the verif team, including the RVFI idea....

**Tracer** this is related to the RVFI-like interface. Currently the Tracer is located in the cv32e40p repo. With a well defined interface we could move the Tracer into core-v-verif and...

> Create more abstract CSR checking interface to enable checking of CSRs with any of the following: Read/Write from instructions or hardware-writable updates I like this idea. @datum-dpoulin has expressed...

Please refer to issue #439 for a more focused discussion of the Tracer/RVFI.

The team at SiLabs reported the following: **functional coverage of operand on individual instructions is missing**. For example, the coverage model itself had no idea if we actually did a...

The treshhold is user-configurable via the 'minNofTokens' parameter in the [ruleset](https://github.com/openhwgroup/core-v-verif/blob/master/vendor_lib/verissimo/ruleset.xml) file. Example of usage: ``` ```