Scott Mabin
Scott Mabin
Builds on top of #2151 Supercededes #1965 Closes https://github.com/probe-rs/probe-rs/issues/1963. I still notice some oddities, where the probe/dtm becomes unresponsive, particularly after flashing once. I usually then need to physically unplug...
This issue aims to track the progress of adding Xtensa support to probe-rs, in particular the Xtensa esp targets. - [x] Initial Xtensa support, Xdm communication with halt/resume and memory...
For RISCV and Xtensa, it is possible to debug multiple cores (unsure about how ARM works, if anyone can fill this information in that would be great), however, they work...
See: https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/algorithmFunc.html#Verify. This is useful with chips that don't have flash mapped to an address space at boot (any esp32 chip, and more advanced processors). Verification is currently achieved by...
The `esp32c3` is a riscv based cpu, _without_ the atomic extension. Unlike the arm `thumbv6` target, it does _not_ have atomic load/stores for the following types `u8`, `u16`, `u32`, which...
I'm slowly working towards the first embedded-fatfs release! The biggest changes have been that the device trait and helpers are now outside of embedded-fatfs itself. This means I can *...
## Thank you for your contribution! We appreciate the time and effort you've put into this pull request. To help us review it efficiently, please ensure you've gone through the...
We already were aware of twai, see #1123, but upon switching to eh1 by default, I had to hack in this commit: https://github.com/esp-rs/esp-hal/pull/1313/commits/121dca7e2201ef59657a5f3bd476612aaecc80a1. All of these fixme's and now public...
 The important line here is the > Figure12-2 is a diagram of timer Tx in a timer group Meaning that each timer inside a timer group can configure its...
We have a lot of type information stored with our GPIO types, and I'm wondering if it's valuable to have or not. The traditional use case for typestates is to...