Zhili Xiong

Results 4 issues of Zhili Xiong

I used RapidWright's readCheckpoint and writeCheckpoint to convert ISPD16's FPGA05 and FPGA09 benchmarks' old DCP to newer version of DCP. But when I run open_checkpoint on vivado2022.1 to open the...

I tried to use PhysicalNetlistToDcp to convert my placments in IF to DCP, and I commented off the xdc input requirement. ``` zhilix@eda15:/home/local/eda15/zhilix/projects/RapidWright$ java com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp FPGA01_rapidwright.netlist example_FPGA01_placement.phys example_FPGA01_rapidwright.dcp Exception in...

I made some changes to the PhysicalNetlistToDcp.java, just to test the intra-site routing: ``` package com.xilinx.rapidwright.interchange; import java.io.File; import java.io.IOException; import java.nio.charset.Charset; import java.nio.file.Files; import java.util.List; import java.util.*; import com.xilinx.rapidwright.design.Design;...

I built the repo and ran the command trying to convert a physical netlist IF to a .json file: ```python3 -m fpga_interchange.convert \ --schema_dir "/home/local/eda15/zhilix/projects/RapidWright/interchange/fpga-interchange-schema/interchange" \ --schema physical \ --input_format...