Dujiao

Cross Trigger definition in RISC-V

3

Since RV doesn't define the cross trigger, can we just consider the external trigger as cross trigger? But what is the type of external trigger, I didn't see in the...

How to halt or resume multiple harts simultaneously?

4

For multi-hart System-on-Chip (SoC) system, which every Debug Module (DM) corresponds to one hart, how can multiple harts be simultaneously halted or resumed synchronously? Thanks!

The way of storage for CS (Configuration Structure) and mconfigtr CSR

1

1. What are the requirements or suggestions for the CS storage method: RAM, ROM, or non-volatile efuse? 2. Is the mconfigtr CSR burned into efuse after tape-out? or it is...

From the spec "However, so long as the same software (e.g. an operating system or machine monitor) is in control at both endpoints of an IPI, source and destination, there...

What is the difference between confstrptr0~3 registers and mconfigptr?

5

The confstrptr0~3 from debug spec includes the address of configuration structure, and so is the definition of mconfigptr from the privileged spec. What is the difference between them?

The current version includes only the discovery of DM and Core. Is it planned to release the discovery of SoC debug & trace components? like SMEM, FUNNEL, Encoder etc.

Can AIA only support 2047 EIID maximum?

3

The IMSIC interrupt file supports 2047 interrupts maximum, that is, the range of External Interrupt Identity (EIID) is 1~2047. What should be done if more interrupt IDs are required? The...