zeicold
Results
2
issues of
zeicold
```verilog module wire_logic ( output logic a, input wire b ); wire logic tie_zero_c; assign tie_zero_c = 1'b0; assign a = b; endmodule ``` verible-verilog-syntax reports: `syntax error, rejected "logic"...
rejects-valid syntax
Seems PySide2 is supported but not PySide6. Is there any plan supporting PySide6?
question