zbjxb
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zbjxb
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你好，作为外行我有个问题：如果B的变化是在CLK的高电平发生时，race condition看起来照样会发生啊？是不是时序电路里有规定逻辑门组件的输入端的变化必须在CLK低电平时发出？
@zhangyachen 哦哦，谢谢
I had the same problem