Zachary Snow
Zachary Snow
sv2v's internal representation wasn't necessarily designed with this feature in mind (it's better suited for the conversion logic). The possible ways of supporting this feature I have considered so far...
@Willyarma Have you had the chance to look at my response above?
> I have not tried the -v option, apologies if this already does what I described. Indeed `--verbose` already accomplishes at least part of (2) in your list (specifically, "matching...
Is there any way to model this sort of bidirectional assignment in portable Verilog? If not, I believe this will be fairly difficult to implement for the general case.
sv2v-generated Verilog code triggers Yosys error: "Insufficient number of array indices for entries"
Can you please try passing `-Ealways` to sv2v? With that conversion disabled, Yosys can fully read the output, though there are warnings that may be relevant.
There are a few different confusions here (my fault): 1. Though the first sentence in the readme already states sv2v has "an emphasis on supporting synthesizable language constructs", this may...
@HakamAtassi Has your question been adequately answered? If so, may I close this issue?
Thank you for reporting these issues! > I'm getting the message "sv2v: too many bindings specified for parameter overrides in instance "c" of "controller" CallStack (from HasCallStack): error, called at...
> The issue has now disappeared after I played around with the source code. I suspect there were two definitions of "controller", one with a parameter and one without. I...
> When using SV interfaces, sv2v likes to produce lots of hierarchical references. Makes sense as it keeps things similar to the original code. The motivating factor was really ease...